1. Field of the Invention
The present invention relates to a clock selection circuit for selecting one clock generator out of a plurality of clock generators of different frequencies, and more particularly, to a clock selection circuit which can eliminate short clock signals when switching clock signals produced by one clock generator to clock signals produced by another clock generator.
2. Description of the Prior Art
Clock selection circuits are frequently used in systems which require two or more clock frequencies such as CD-ROM (compact disc xe2x80x94read only memory) player. A CD-ROM player usually requires a high frequency clock for reading text data and a low frequency clock for reading audio signals from a CD-ROM. A clock selection circuit is required for selecting clock signals generated from the high frequency or low frequency clock.
Please refer to FIG. 1. FIG. 1 shows a prior art clock selection circuit 10 which is connected to two clock generators F1 and F2. Circuit 10 is controlled by a clock selection signal inputted from port S. Circuit 10 comprises an inverter 12 for inverting the clock selection signal inputted from port S, an AND gate 14 connected to the clock generator F1 and port S, an AND gate 16 connected to the clock generator F2 and the inverter 12, and a NOR gate 18 connected to the outputs of the AND gates 14 and 16 for producing the output clock signals Fout. The two clock generators F1 and F2 are used to generate clock signals of different frequencies, but only the clock signals of one clock generator will be selected by the clock selection circuit 10 according to the clock selection signal inputted from port S.
Please refer to FIG. 2. FIG. 2 is a timing diagram of the clock selection circuit 10 shown in FIG. 1. It shows the clock signals generated by the two clock generators F1 and F2, the clock selection signal inputted from port S, and the clock signals Fout outputted from NOR gate 18 of the clock selection circuit 10. Each clock signal comprises two logic levels: a logic high and a logic zero. And the clock frequency of the clock generator F1 is higher than the clock frequency of the clock generator F2. One problem of the prior art clock selection circuit 10 is clearly shown in the timing diagram. Before the clock selection signal 20 is received, the clock signals outputted from NOR gate 18 is generated by the clock generator F2. And after receiving the clock selection signal 20, the output of the NOR gate 18 is switched to the clock signals generated by the clock generated by the clock generator F1. The period of the clock signal 22 which is generated when the output of the NOR gate 19 is switched from clock generator F2 to F1, is much shorter than any of the clock signals generated by the clock generators F1 or F2. Such short clock signal may cause abnormal behavior of the logic circuit of a CD-ROM player since the logic circuit is designed to fit clock rates up to the clock rate of the clock generator F1. If a clock signal of much higher clock rate, such as the clock signal 22, is passed to the logic circuit, the logic circuit may not tolerate such high frequency clock signal and the result is unpredictable. It may cause failure in reading data from a CD-ROM or may cause damage to the CD-ROM player.
It is therefore a primary objective of the present invention to provide a clock selection circuit which can eliminate short clock signals when switching clock signals generated by one clock generator to the clock signals generated by another clock generator.
In a preferred embodiment, the present invention includes a clock selection circuit comprising:
selecting means for selecting the clock signals generated by a first clock generator out of a plurality of clock generators of different frequencies and generating an output, each clock signal comprising two different logic levels;
first detecting means for detecting a predetermined logic level contained in the output of the selecting means after receiving a clock selection signal wherein the selecting means is switched to select the clock signals generated by a second clock generator according to the clock selection signal after the predetermined logic level is detected by the first detecting means;
holding means for holding the output of the selecting means unchanged after the predetermined logic level being detected by the first detecting means; and
second detecting means for detecting the predetermined logic level contained in the output of the selecting means after the output of the selecting means being held by the holding means and releasing the holding means to allow the output of the selecting means to pass through when detected.
The first detecting means detects the predetermined logic level contained in the output of the selecting means when a leading edge of the predetermined logic level is detected by the first detecting means. And the second detecting means detects the predetermined logic level contained in the output of the selecting means when a leading edge of the predetermined logic level is detected by the second detecting means.
It is an advantage of the present invention that the output of the clock selection circuit generated by the holding means is maintained in the predetermined logic level after the predetermined logic level generated by the first clock generator is detected by the first detecting means, and the holding means is released by the second detecting means to allow the output of the selecting means to pass through after the predetermined logic level generated by the second clock generator is detected by the second detecting means. When the clock signals generated by the first clock generator is switched by the clock selection circuit to the clock signals generated by the second clock generator, the output of the clock selection circuit will be maintained in the predetermined logic level which guarantees that the period of the clock signal generated at the switching period will never be shorter than the period of the clock signals generated by the second clock generator. In such case the above mentioned short clock signal problem is totally solved.